1. Field of the Invention
This invention generally relates to a multi-chip module (MCM), and more particularly to a multi-chip module having a stacked chip arrangement.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the packages for protecting and interconnecting IC chips have the same trend, too.
With ever increasing demands for miniaturization and higher operating speeds, multichip modules (MCMs) are increasingly attractive in a variety of electronics. MCMs which contain more than one die can help minimize the system operational speed restrictions imposed by long printed circuit board connection traces by combining, for example, the processor, memory, and associated logic into a single package. In addition, MCMs decrease the interconnection length between IC chips thereby reducing signal delays and access times.
The most common MCM is the "side-by-side" MCM. In this version two or more IC chips are mounted next to each other (or side by side each other) on the principal mounting surface of a common substrate. Interconnections among the chips and conductive traces on the substrate are commonly made via wire bonding. The side-by-side MCM, however, suffers from a disadvantage that the package efficiency is very low since the area of the common substrate increases with an increase in the number of semiconductor chips mounted thereon.
Therefore, U.S. Pat. No. 5,323,060 teaches a multichip stacked device (see FIG. 1) comprising a first semiconductor chip 110 attached to a substrate 120 and a second semiconductor chip 130 stacked atop the first semiconductor chip 110. The chips 110, 120 are respectively wire bonded to the substrate 120. U.S. Pat. No. 5,323,060 is characterized by using an adhesive layer 140 between the two chips to provide clearance between the chips for the loops of the bonding wires 150. The adhesive layer has a thickness greater than the loop height defined by the distance between the active surface of the chip 110 and the vertexes of the outwardly projecting loops of the bonding wires 150 so as to prevent the bonding wires 150 from contacting the chip 130.
Prior art wire bonding techniques make the wire interconnection between the chip bond pad and the substrate contact pad by making a ball bond to the chip bond pad, forming a loop therebetween, and making a stitch bond to the substrate contact pad to finish the wire interconnect. The normal loop height is generally about 10 to 15 mils. As thinner packages have been developed, the loop height has been reduced with conventional bonding techniques down to about 6 mils in height by changes in the loop parameters, profile and wire types. However, this loop height is considered to be a minimum obtainable loop height as attempts to go lower have caused wire damage and poor wire pull strengths.
Therefore, using this conventional bonding technique, the adhesive layer 140 must have a thickness of at least 8 mils to prevent the chip 130 from contacting the bonding wires 150. Typical materials for the adhesive layer 140 include epoxy and tape. However, it is very difficult to form an epoxy layer with a stable bond line thickness above 3 mils. Further, even using a tape with a thickness of 8 mils, it will increase the cost of the final product, and the reliability of resulted package will suffer from the CTE mismatch between thermoplastic tape and silicon chip.
The loop height can be reduced to about 0.002 inches by the use of an entirely different wire bonding technique disclosed in U.S. Pat. No. 5,735,030. Referring now to FIGS. 2 and 12, there is shown a process flow for wire bonding in accordance with U.S. Pat. No. 5,735,030. Initially, as shown in FIG. 12, a protuberance 200 is formed on the chip bond pad 210 by first ball bonding the free end of an electrically conductive wire onto the chip bond pad 210, and thereafter stitch bonding the same wire to its ball bonded end at a point on the wire immediately adjacent the ball bonded end such that the ball bond and stitch bond together form the protuberance 200. Then, using a ball bonding tool, first ball bonding one end of a bonding wire 220 to the substrate contact pad 230 and thereafter stitch bonding the other end of the bonding wire 220 to the protuberance 200 on the chip bond pad 210 (see FIG. 2).
Referring to FIG. 1 and FIG. 2, if the bonding wires 150 are formed by the wire bonding technique disclosed in U.S. Pat. No. 5,735,030, the adhesive layer 140 must have a thickness of at least 4 mils to prevent the chip 130 from contacting the bonding wires 150. However, it is very difficult to form an epoxy layer with a stable bond line thickness above 4 mils. Once the bond line thickness is not stable, it will introduce unsatisfactory coplanarity of the upper chip 130, after mounting of the upper chip 130. Sometimes the bond line thickness is so uneven to cause the chip 130 to come in contact with the loop profile of the lower bonding wires thereby resulting in deformation or shift of the loop profile of the lower bonding wires.